<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>PMCCIDSR</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMCCIDSR, CONTEXTIDR_ELx Sample Register</h1><p>The PMCCIDSR characteristics are:</p><h2>Purpose</h2>
        <p>Contains the sampled value of <a href="AArch64-contextidr_el1.html">CONTEXTIDR_EL1</a> and <a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>, captured on reading PMU.PMPCSR.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCCIDSR are <span class="arm-defined-word">RES0</span>.</p>
        <p>If FEAT_PMUv3_EXT32 is implemented, the same content is present in the same location, and can be accessed using PMCID2SR[31:0] and PMCID1SR[31:0].</p>

      
        <div class="note"><span class="note-header">Note</span><p>If <span class="xref">FEAT_PCSRv8p2</span> is not implemented, the PC Sample-based Profiling Extension can be implemented in the external debug register space, as indicated by the value of <a href="ext-eddevid.html">EDDEVID</a>.PCSample.</p></div>
      <h2>Attributes</h2>
        <p>PMCCIDSR is a 64-bit register.</p>
      <p>This  register is part of the <a href="pmu.html">PMU</a> block.</p><h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_32">CONTEXTIDR_EL2</a></td></tr><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">CONTEXTIDR_EL1</a></td></tr></tbody></table><h4 id="fieldset_0-63_32">CONTEXTIDR_EL2, bits [63:32]</h4><div class="field"><p>Context ID. The value of <a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a> that is associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample is generated:</p>
<ul>
<li>If the PE is not executing at EL3, EL2 is using AArch64, and EL2 is enabled in the current Security state, then this field is set to the Context ID sampled from <a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>.
</li><li>Otherwise, this field is set to an <span class="arm-defined-word">UNKNOWN</span> value.
</li></ul>
<p>Because the value written to this field is an indirect read of <a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>, it is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> whether this field is set to the original or new value if PMU.PMPCSR samples:</p>
<ul>
<li>An instruction that writes to <a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>.
</li><li>The next Context synchronization event.
</li><li>Any instruction executed between these two instructions.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-31_0">CONTEXTIDR_EL1, bits [31:0]</h4><div class="field"><p>Context ID. The value of <span class="xref">CONTEXTIDR</span> that is associated with the most recent PMU.PMPCSR sample. When the most recent PMU.PMPCSR sample is generated:</p>
<ul>
<li>If EL1 is using AArch64, then the Context ID is sampled from <a href="AArch64-contextidr_el1.html">CONTEXTIDR_EL1</a>.
</li><li>If EL1 is using AArch32, then the Context ID is sampled from <a href="AArch32-contextidr.html">CONTEXTIDR</a>.
</li><li>If EL3 is implemented and is using AArch32, then <a href="AArch32-contextidr.html">CONTEXTIDR</a> is a banked register and this register samples the current banked copy of <a href="AArch32-contextidr.html">CONTEXTIDR</a> for the Security state that is associated with the most recent PMU.PMPCSR sample.
</li></ul>
<p>Because the value written to this register is an indirect read of <span class="xref">CONTEXTIDR</span>, it is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span> whether this register is set to the original or new value if PMU.PMPCSR samples:</p>
<ul>
<li>An instruction that writes to <span class="xref">CONTEXTIDR</span>.
</li><li>The next Context synchronization event.
</li><li>Any instruction executed between these two instructions.
</li></ul><p>The reset behavior of this field is:</p><ul><li>On a Cold reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing PMCCIDSR</h2>
        <p><span class="arm-defined-word">IMPLEMENTATION DEFINED</span> extensions to external debug might make the value of this register <span class="arm-defined-word">UNKNOWN</span>, see <span class="xref">'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'</span>.</p>
      <p>Accesses to this register use the following encodings:</p><h4 class="assembler"><span class="condition">
When FEAT_PMUv3_EXT64 is implemented
        </span><br/>Accessible at offset 0x228 from PMU</h4><ul><li>When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RO</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
